| Length | 280 |
|---|---|
| Seed | 1 |
| Weight | 35 |
| Vector |
01010000110000000000000000100010000111000000000111 00000100000001000000000000000000000001000001000000 00000010000000000000000000001000000011000001110000 00000000000000100001000000000000010000100000000000 00000000000000010001000000000000000000000000100010 000101000000000000000100000001 |
| Authors | Ante Silovic |
| Algorithm | Prange |
| Hardware | Cyclone V GX Starter Kit (FPGA) |
| Runtime | 13 hours 5 minutes |
| Comments | Logic utilization (in ALMs) 19,755 / 29,080 ( 68 % ) Total registers 19784 Total pins 21 / 364 ( 6 % ) Total virtual pins 0 Total block memory bits 2,319,596 / 4,567,040 ( 51 % ) Total DSP Blocks 46 / 150 ( 31 % ) Total HSSI RX PCSs 0 / 6 ( 0 % ) Total HSSI PMA RX Deserializers 0 / 6 ( 0 % ) Total HSSI TX PCSs 0 / 6 ( 0 % ) Total HSSI PMA TX Serializers 0 / 6 ( 0 % ) Total PLLs 0 / 12 ( 0 % ) Total DLLs 0 / 4 ( 0 % ) Fmax 120.03 MHz 120.03 MHz CLOCK_50_B5B (ran at 50mhz) |
| Date | 2026-07-29 |